uxI9Za3IJBzv2WTOjUkCzl0Hd0CUfvb8tEAx2HtefLR7qebVwOAH48BcDldi
Current position: Home >> Scientific Research >> Paper Publications

A Low-Power DNN Accelerator with Mean Error Minimized Approximate Signed Multiplier

Hits:

Title of Paper:A Low-Power DNN Accelerator with Mean Error Minimized Approximate Signed Multiplier

Journal:IEEE Open Journal of Circuits and Systems (OJCAS)

Translation or Not:No

Date of Publication:2024-04-11

Date:2024-07-11

Prev One:A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators

Next One:A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC